Digital logic gates typically incorporate p-type metal oxide semiconductor (MOS) transistors, which are used for precharging and storage in dynamic complementary metal oxide semiconductor (CMOS) logic. Dynamic CMOS circuits are susceptible to noise due to capacitive coupling or leakage current from MOSFETs. These phenomena adversely affect circuit operation since the circuit output is not held by a conducting MOSFET on removal of the input signal. Another problem with dynamic CMOS gates is charge sharing which reduces the output high voltage possibly causing logic errors.
Researchers at the University of Michigan developed digital logic gates, also referred to as quantum MOS or QMOS logic gates, which include bistable mode circuits using negative differential resistance (NDR) diodes and metal oxide semiconductor field effect transistors (MOSFETs). The NDR diode, which acts as a pull up load and latching element, eliminates the need for pMOS transistors used in prior dynamic logic gates for precharging and storage. The NDR diode helps eliminate some of the problems associated with prior designs by continually maintaining the output node voltage at a value dictated by the logic at the time of evaluation. The faster switching speed of NDR diodes also increases the speed of operation of the logic gates of the present invention allowing compact, higher speed implementations having improved power-delay products over conventional implementations.
Applications and Advantages
- Digital logic gate design
- Improved performance due to compact logic design
- Elimination of a pipeline latch area and delay overheads