Office of Technology Transfer – University of Michigan

Technique for Reduced-tag Dynamic Scheduling

Technology #2301

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Todd M. Austin
Managed By
Joohee Kim
Licensing Specialist, Physical Sciences & Engineering 734-764-8202
Patent Protection
US Patent Pending


In an effort to secure higher levels of system performance, microprocessor designs often employ dynamic scheduling as a technique to extract instruction level parallelism from serial instruction streams. Conventional dynamic scheduler designs house a “window” of candidate instructions from which ready instructions are sent to functional units in an out-of-order data flow fashion. The instruction window is implemented using large monolithic content addressable memories that track instructions and their input dependencies. This design requires the tracking of tag comparisons necessary to schedule instructions, and is therefore responsible for an increasingly large portion of latency in high-performance microprocessors. In addition to performance issues, power dissipation has also become an increasing concern in the design of high-performance microprocessors. Increasing clock speeds and diminishing voltage margins have combined to produce designs that are increasingly difficult to cool. Studies have shown that the scheduler logic consumes a large portion of a microprocessor’s power and energy budgets, making the scheduler a prime target for power optimizations.


Researchers at the University of Michigan have observed that most scheduler tag comparisons are superfluous to the correct operation of the instruction scheduler. Therefore, the performance of the scheduler can be improved by decreasing the number of tag comparisons necessary to schedule comparisons. Two scheduler tag-reduction techniques are introduced, which together work to improve the performance of dynamic scheduling and reduce power requirements. By combining these two tag-reduction schemes, researchers have been able to construct dynamic schedulers with approximately one quarter of the tag comparators found in conventional designs. Conservative circuit-level timing analyses indicate that the optimized designs are 20-45% faster and require 10-25% less power, depending on instruction window size. Furthermore, combining this tag-elimination design with other research efforts to reduce the complexity of dynamic scheduler may yield even more efficient results.

Applications and Advantages


  • Microprocessor systems


  • Faster and more efficient dynamic-nl-scheduling performance