Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits must be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology.
Researchers at the University of Michigan have developed a method and apparatus to improve noise tolerance of dynamic circuits. The circuits include a power supply node and a precharge node. Keeper circuitry is connected to the nodes and has a current-voltage characteristic that exhibits a negative differential resistance property to improve noise tolerance of the circuits. The method also includes substantially maximizing peak current along the circuit path to improve noise tolerance of the dynamic circuit and substantially minimizing average current along the circuit path to reduce performance overhead due to the keeper circuitry. The size of the keeper transistor plays a very important role in both the correct logical function as well as the speed of a dynamic stage in CMOS circuits. This new keeper maintains all previous advantages of dynamic logic, and has managed to improve upon the noise margin inefficiencies in conventional dynamic design. It has been designed using a 0.18 mm process, tested at a supply voltage of 1.6 V and at 55ºC.
Applications and Advantages
- Keepers for improving noise tolerance of dynamic logic circuits
- Very little overhead in area, circuit speed, and power consumption