Office of Technology Transfer – University of Michigan

Low-Power Area-Efficient SAR ADC

Technology #4494

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Euisik Yoon
Managed By
Joohee Kim
Licensing Specialist, Physical Sciences & Engineering 734.764.8202
Patent Protection
US Patent 8,797,204


In the monitoring of neural activity, simultaneous, real-time monitoring of multiple neural sites in 3 dimensional electrode arrays is ideal. Towards this end, recent development in neural probes includes the implementation of multichannel neural interface systems. In microsystems, the neural signals are often amplified and converted into digital signals for transmission via wired/ wireless communication channels between the implanted system and the external world. Simultaneous access of multiple sites requires better noise immunity in analog-to-digital converters (ADC) in a small form factor at low power. A successive approximation register (SAR) ADC is one of the suitable candidates for neural interface applications due to its simplicity, low power consumption, and reasonable resolution. However, as capacitor arrays of current ADCs at high resolutions occupies most of the area and consumes much power, and it becomes more important to reduce the total capacitance and area as the number of bits required in ADC increases and multiple implementations of ADCs is needed.


University of Michigan researchers have developed an area-efficient 8 bit SAR ADC using dual capacitor arrays. Using the dual capacitor array banks, the required capacitor array area has been reduced, and ADCs have been effectively implemented within the given area and power budget. Compared to a conventional ADC, the proposed ADC occupies 80% less space and consumes 85% less power. In addition, no indications of leakage were observed.

Applications and Advantages


  • Successive approximation register analog-to-digital converters for neural interface systems


  • Reduced required capacitor array area
  • Lower power consumption through elimination of power required for charging/discharging