Single and few-layer graphene are promising materials for post-silicon electronics, owing to their potential of integrating bottom-up nanomaterial synthesis with top-down lithographic fabrication. However, as single-layer graphenes are intrinsically semi-metals, introducing energy bandgap to these materials requires patterning nanometer-width graphene ribbons or utilizing special substrates. In contrast, bilayer graphene has an electric field-induced bandgap, as well as exciton binding energies, which are tunable with electric field, opening new possibilities of bilayer graphene-based electronics and photonics. To date, most bilayer graphene samples are fabricated using mechanical exfoliation of graphite, which limits the size of the resulting sample to a micron scale, and is not scalable. While recent developments in chemical vapor deposition (CVD) methods have successfully produced large scale, single-layer graphene on metal substrate, the synthesis of uniform, bilayer graphene product on a wafer-scale presents a tremendous challenge.
University of Michigan researchers have developed a method of producing uniform multilayer graphene films that are greater than square cm in area. In this method, multilayer graphene is produced as-deposited by a single CVD process, eliminating the need to produce multiple separate monolayers followed by stacking. Bilayer coverage was shown to be >99%, as confirmed by spatially resolved Raman spectroscopy. Electrical transport measurements on dual-gate bilayer graphene transistors demonstrated that field-induced bandgap opening was observed in at least 98% of the devices. Using this approach, the size of fabricated bilayer graphene film is only limited by the synthesis apparatus, and can be readily scaled up, enabling wafer-scale graphene electronics and photonics.
Applications and Advantages
- Graphene electronics and photonics
- Scalable process, applicable to synthesis of wafer-scale multilayer graphene films
- Potential improvement in device performance, enabled by use of high-k dielectrics for gates via CVD process