Post-Silicon Validation Electronic technologies’ increasing dependence on processing capabilities necessitates efficient and effective verification of the processor design (pre-silicon validation) and physical prototype (post-silicon validation). In developing a design, the operation can be simulated with great control of the test paths and the deterministic transparency allows bugs to be pinpointed easily. Material non-idealities, fabrication inconsistencies and unforeseen interactions between devices or testing conditions on a physical chip make post-silicon validation an essential step in bringing a chip to market. The increasing complexity and size of chips is shifting the importance from the time and computational intensive pre-silicon validation to the statistical testing of post-silicon validation. Unfortunately, many bugs are asynchronous or intermittent throughout operation making them very difficult and time consuming to detect and rectify.
BPS (Bug Positioning System) Researchers at the University of Michigan have developed a post-silicon validation method that effectively detects and locates, in both time and space, intermittent bugs that would otherwise be very difficult to rectify. Their method provides a robust platform for testing whole chipsets to detect functional, electrical and manufacturing bugs with both high spatial and time resolution decreasing the time necessary to fix the inconsistencies. Through the use of flexible data collection window lengths, allowing optimization of off-chip data transfers, responsiveness to atypical device characteristics and a new post-processing procedure, BPS provides the ability to improve post-silicon validation to detect intermittent bugs that traditionally have been very difficult to detect.
Applications • Post-silicon validation • SoC (System-on-Chip) bug detection and localization
Advantages • Accurate bug localization in time and space