Office of Technology Transfer – University of Michigan

A Photodetector Based on Double Layer Heterostructures

Technology #5456

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Researchers
Zhaohui Zhong
Managed By
Joohee Kim
Licensing Specialist, Physical Sciences & Engineering 734.764.8202
Patent Protection
US Patent Pending

University of Michigan’s Low-Cost, High-Performance, CMOS-Compatible Photodetector Architecture

Researchers at the University of Michigan have developed a low-cost, high-responsivity, broad-spectrum photodetector that is compatible with CMOS manufacturing processes. Photodetectors with high responsivity and broad-spectrum detection are desirable for imaging or sensing applications. High-responsivity photodetectors or light detectors are typically realized using avalanche photodetectors or photomultipliers. However, since avalanche photodetectors or photomultipliers are bulky and require high external bias voltages, integration with existing silicon-based technologies and/or manufacturing on-chip imaging arrays is challenging. An alternative approach involves using phototransistors. But high-responsivity phototransistors require high-cost epitaxial growth processes or low device operation temperatures, thereby limiting the applications of these phototransistors.

Technical Details

The photodetector architecture developed at the University of Michigan overcomes the issues listed above. The design includes two closely spaced light-absorbing material layers separated by a thin-film insulator. Without light excitation and voltage bias, each light-absorbing layer is electrically isolated from the other. However, under optical excitation, both layers generate photoexcited electron-hole pairs. With back-gate biasing, the insulator layer serves as the hole blocking layer causing photoexcited electrons to tunnel into the bottom light-absorbing layer, leaving behind positively charged holes in the top light-absorbing layer

Applications

  • Photodetectors
  • Image Sensing Applications

Advantages

  • High responsivity
  • Simple planar device structure
  • Small footprint
  • CMOS-compatible fabrication
  • Support for on-chip integration
  • Low cost (does not require high-cost doping or epitaxial growth)