Office of Technology Transfer – University of Michigan

13T SRAM Cell for Improving Write Margin in Ultra-Low Power Applications

Technology #5937

Subthreshold Static Random Access Memory (SRAM) operation can produce enormous power savings, but at the expense of decreased data reliability. Low power operation makes SRAM more susceptible to electrical noise and interference and lowers read and write margins. Researchers at the University of Michigan have developed a new 13T SRAM cell technology for subthreshold operation that demonstrates significantly improved write margins and reduced power usage at high reliability levels.

Static write operations save power and improve reliability

The 13T SRAM allows for static operation of the memory cell during write, reducing power usage and sources of noise and increasing the write margin. Simulations have been validated and demonstrate improved performance over standard 6T and 8T SRAM designs, with 40% less power dissipation during read and up to 36% less power dissipation during write for the same margin requirements. This could prove to be a boon in ultra-low power processors that also require highly reliable onboard cache and memory.


  • Microcontrollers memory
  • Ultra-low power processors cache


  • Higher write margins increases robustness to noise and interference
  • Lower power usage for given write margin requirements
  • Static design allows for easier component sizing and lower design costs