With a rapid increasing demand of high performance chips for mobile applications, single chips are expected to perform highly diversified functions, which shifts the integrated circuit design towards large chip multi-processors (CMP) and system-on-chip (SoC) design consisting of mulitple cores and integrated processors using a network-on-chip (NoC) for communication. Due to the increasing concerns of transistor reliability and transistor counts, a reliable NoC should tolerate significant amount of permanent faults. However, current state-of-art NoC solutions still cannot fulfill the demand of SoC.
High performance NoC fault-tolerance architecture
U-M researchers demonstrate a unified framework for permanent fault diagnosis and subsequent reconfiguration in NoCs that provides graceful performance degradation with increasing number of faults. The experimental results show that the new NoC solution can drop few nodes and provide 25% higher throughput when compared to other state-of-the-art fault-tolerance solutions. These results show that the new NoC architecture is a reliable solution for a wide range of fault rates.
- SoC chips for mobile devices
- High performance computing
- Better fault-tolerance solutions