The aging Von Neumann architecture is no longer effective at fulfilling modern computing demands and recent advances in non-volatile memories such as resistive memory (RRAM) devices can redefine the classical computer architecture. For decades, advances in computer performance were directly related to the scaling of Complementary metal–oxide–semiconductor (CMOS) transistors according to Moore’s law. However, both the CMOS scaling and classical computer architecture are approaching their limits.
A reconfigurable, scalable, energy-efficient, and highly parallel computing system
This technology relates to a next generation architecture, which is memory-centric, reconfigurable, and general-purpose computing platform to handle the exploding amount of digital data in a fast and energy-efficient manner. This is not achievable without reducing the amount of slow and power-hungry communications between the memory and processor, and overcoming the memory wall barrier. In addition, computing should be natively parallel at a fine-grain level, and it is desirable for a new computing architecture to have analog computing capabilities, to allow better handling of analysis, classification, and recognition task. To achieve these desirable properties, a novel computing architecture, where a single physical memory-centric platform is optimally utilized to perform different computing and data storage jobs in a massively native and parallel manner, has been developed. This system is dynamically reconfigured based on the data types to optimally allocate the basic computing fabric to storage, arithmetic, and analog computing tasks.
- Smart sensor nodes
- Server farms
- Highly parallel